With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, semiconductor devices, such as transistors, diodes, capacitors and the like, need ever more complex and densely packaged electrical interconnection systems between devices. The conventional process of manufacturing such interconnection systems has been to use a series of lithographic processes to pattern and dispose metal interconnection lines and vias on a dielectric layer to form a metallization layer. The metallization layer would be disposed above a substrate having active semiconductor devices embedded therein and the interconnection system would provide the contacts and interconnections between those devices.
Previously, the lithography process was carried out on a two-dimensional (2D) scale, that is, on a single metallization layer, wherein geometrically complex patterns were disposed on one level to form the interconnections between devices. However, at about a pitch of 90 nanometers (nm), the resolution of current lithographic processes becomes blurred enough to make such complex patterning unreliable. This is especially the case in the first two metallization layers (M1 and M2) where metallization is the densest.
Therefore, as illustrated in exemplary prior art FIG. 1, at lower technology class sizes, such as the 10 nm class and lower, self-aligned double patterning (SAPD) processes are now used to provide an interconnection system 10 which includes multiple levels of arrays of parallel pairs of straight metalized trenches (or interconnect lines) 12 and 14 disposed in dielectric layers 16. The array of interconnect lines 12 and 14 of each dielectric layer 16 are often oriented at 90 degree angles relative to the arrays of the adjacent dielectric layers (not shown). The multiple dielectric layers are connected with a system of vias, such that, once the trenches and vias are metallized, there is electrical continuity between levels of the interconnection system 10.
In order to provide device functionality, a plurality of non-aligned dielectric blocks 18 and 20, which block the electric continuity of neighboring interconnection lines 12 and 14, are patterned into the dielectric layer at specific locations to direct current flow between the dielectric layers 16 and devices. The blocks 18 and 20 are patterned into the dielectric layer 16 through a series of lithographic processes. In the exemplary ideal case, as shown in FIG. 1, the lithographic processes are perfectly aligned such that block 18 interrupts the precise active interconnect line 12 it is associated with, without extending into any neighboring interconnect line 14. Additionally block 20 interrupts its interconnect line 14 without extending into any neighboring line 12.
Problematically, lithographic misalignment, or overlay, is a significant issue at lower technology node sizes, such as when the technology class size is no greater than 10 nm or when the repetitive pitch distance is no greater than 40 nm. Overlay is a measure of how well two lithographic layers (or steps) align. Overlay can be in the X or Y direction and is expressed in units of length.
In mass production, the lithographically disposed dielectric blocks 18 and 20 must be large enough to make sure that they always cut the active line they are supposed to (i.e., lines 12 and 14 respectively) without clipping any neighboring lines, taking into account the overlay control for the worst 3 sigma case. In an exemplary worst 3 sigma case scenario, as shown in prior art FIG. 2, for at least the 10 nm class or less or for a pitch of 40 nm or less, the current state of the art 3 sigma overlay control is not precise enough to prevent dielectric blocks 18 and 20 from over-extending into active neighboring lines in an acceptably few number of cases. That is, the failure rate of blocks 18 extending into adjacent lines 14 and blocks 20 extending into adjacent lines 12 will be outside of the industry acceptable 3 sigma standard.
The unwanted over-extension of blocks 18 (which are supposed to cut lines 12 only) into neighboring lines 14, and over-extension of blocks 20 (associated with lines 14) into neighboring lines 12 can, in the worst case condition, completely interrupt electrical continuity in the wrong line. Additionally, a line that is inadvertently only partially cut may still conduct for a time, but will over heat and prematurely fail.
Accordingly, there is a need for a method of patterning interconnection lines that is tolerant of lithographic misalignment or overlay. Additionally, there is a need for a method that is capable of patterning dielectric blocks between interconnection lines such that the blocks do not clip neighboring lines.